1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operating at high frequencies in synchronization with a rise and a fall of an external clock and including a preamplifier amplifying data read from a memory cell array to be output to a data bus pair.
2. Description of the Background Art
By demand for a higher frequency operation of a semiconductor device, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) allowing data input/output in synchronization with a rising edge and a falling edge of an external clock has been developed and brought into practical use.
FIG. 10 is a timing chart showing a data output timing in reading data from a DDR SDRAM that is a so-called DDR-I. In this DDR SDRAM, a CAS latency CL is set at 2.0 and a burst length BL is set at four. Here, CAS latency represents the number of cycles (one cycle corresponds to the rise of an external clock CLK to the next rise) required for DDR SDRAM to receive an READ command (a command for reading data) from the outside and then to start to output the read data to the outside. Furthermore, the burst length represents the number of bits successively read in response to READ command.
Referring to FIG. 10, DDR-I outputs data DQ that is the read data and a data strobe signal DQS in synchronization with external clocks CLK, /CLK. Here, external clock /CLK is a clock signal complimentary to external clock CLK. Data strobe signal DQS is a signal for use as a take-in timing of data DQ at an external controller receiving data DQ.
A timing difference tAC between the edges of external clocks CLK, /CLK and the output of data DQ is defined to fall within a certain range. In FIG. 10, timing difference tAC is controlled at zero.
In order to realize a data output as shown in FIG. 10, there is need for an operation clock of which timing is slightly earlier than the timing of the edges of external clocks CLK, /CLK at a data output circuit. This is because a delay occurs from an input of the external clock to the semiconductor memory device to an actual output of data due to the capacity of each circuit which is included in the device.
More specifically, what is required is a clock generation circuit operated in a manner as follows. As external clocks CLK, /CLK are fixed-cycle signals, internal clocks CLK_P, CLK_N shifted backward by an appropriate time Ta with respect to the edges of external clocks CLK, /CLK are generated by delaying external clocks CLK, /CLK by an appropriate delay amount Td. Furthermore, the delay amount Td can be controlled such that data DQ output from the data output circuit operating using these internal clocks CLK_P, CLK_N as a trigger and data strobe signal DQS output from a data strobe signal output circuit satisfy the aforementioned timing difference tAC. A circuit generating such an internal clock is called a DLL (Delay Locked Loop) circuit.
Now, in order to carry out the data output as shown in FIG. 10, a so-called pipeline operation is necessary in which data read from the memory cell array is appropriately shifted in synchronization with internal clocks CLK_P, CLK_N and is finally delivered to an output buffer. More specifically, the data read from the memory cell array sequentially passes through each stage forming a pipeline at an appropriate timing synchronized with internal clocks CLK_P, CLK_N and reaches the output buffer. Although a variety of configurations may be employed as a stage configuration of the pipeline, a first stage may correspond to a segment up until the read data is output to a data bus pair DB and /DB after a preamplifier.
FIG. 11 is a functional block diagram functionally illustrating the circuit configuration from a bit line pair BL and /BL to data bus pair DB and /DB in a case where the segment described above is a first stage of the pipeline.
Referring to FIG. 11, a sense amplifier 50 detects and amplifies data read from the memory cell array (not shown) onto bit line pair BL and /BL. Thereafter, a decode signal YA corresponding to an externally received column address goes to H (logic high) level. After an appropriate delay time period, a column decode enable signal CDE for activating a column select line CSL goes to H level. Accordingly, the output of an AND gate 108 goes to H level and one column select line CSL corresponding to the column address is selected. Then data is output at small amplitude from sense amplifier 50 through N-channel MOS transistors N1, N2 onto an I/O line pair LIO and /LIO. It is noted that an I/O equalizer 102 is a circuit equalizing I/O line pair LIO and /LIO at H level in advance before data is output onto I/O line pair LIO and /LIO. Then, the data on I/O line pair LIO and /LIO is input to a preamplifier 148.
Preamplifier 148 includes an amplifier circuit 222, a latency shifter 124 and a driver 126. Here, latency shifter 124 configures a data shift circuit.
Amplifier circuit 222 resets the internal state based on a signal PACL output from a delay circuit 104 and amplifies a small amplitude signal on I/O line pair LIO and /LIO by a differential amplifier included therein based on a signal PAEL output from a delay circuit 106. Amplifier circuit 222 then outputs the amplified signal onto data line pair PD3 and /PD3.
Latency shifter 124 holds data received from data line pair PD3 and /PD3 until a signal RDT goes to H level, and outputs the data onto data line pair PDD and /PDD at a timing when signal RDT goes to H level. Driver 126 outputs data received from data line pair PDD and /PDD onto data bus pair DB and /DB at small amplitude.
Here, signal RDT received by latency shifter 124 is a signal that determines the timing at which data is moved from a first stage to a second stage in the pipeline operation, and determines the timing at which the data amplified by amplifier circuit 222 is output onto data bus pair DB and /DB. Signal RDT is generated by a control circuit (not shown), starting from a clock cycle following a clock cycle that is a starting point of reading corresponding data from the memory cell array.
Delay circuit 104 receives column decode enable signal CDE and outputs signal PACL produced by delaying column decode enable signal CDE by an appropriate amount to delay circuit 106 and to amplifier circuit 222 in preamplifier 148. This signal PACL provides a timing for resetting the internal state in preamplifier 148. Delay circuit 106 receives signal PACL output from delay circuit 104 and outputs signal PAEL produced by delaying signal PACL by an appropriate amount to amplifier circuit 222. This signal PAEL provides a timing for amplifying the signal received from I/O line pair LIO and /LIO in amplifier circuit 222 in preamplifier 148 for output to latency shifter 124.
FIGS. 12-16 are circuit diagrams showing a circuit configuration of amplifier circuit 222. Amplifier circuit 222 includes an input processing circuit 132, a PAE generation circuit 234, a CLRES generation circuit 136, a /PAEC generation circuit 138 and an amplify/output circuit 240.
Referring to FIG. 12, input processing circuit 132 includes an inverter 1322, an NAND gate 1324 and an NOR gate 1326. A signal /PAEQ generated in response to signal PACL output from delay circuit 104 is a signal for equalizing differential amp nodes PAN, /PAN in amplify/output circuit 240 described later. Signal PADT generated in response to signal PAEL output from delay circuit 106 is a signal being at H level from H level of signal PACL to H level of signal PAEL, for connecting differential amp nodes PAN and /PAN to I/O line pair LIO and /LIO to take in data on I/O line pair LIO and /LIO into preamplifier 148, in amplify/output circuit 240 described later.
Referring to FIG. 13, PAE generation circuit 234 includes inverters 2342-2346. Signals PAE, /PAE generated in response to signal PAEL are signals for activating a differential amplifier included in amplify/output circuit 240 described later.
Referring to FIG. 14, CLRES generation circuit 136 includes an NOR gate 1362 and an inverter 1364. Here, a signal /ACT is received from the control circuit (not shown) and goes to L (logic low) level when rows are activated. A signal CLRES generated in response to signal PACL is a signal for resetting a latch circuit on a stage following the differential amplifier included in amplify/output circuit 240 described later.
Referring to FIG. 15, /PAEC generation circuit 138 includes an NOR gate 1382. A signal /PAEC is a signal for activating the latch circuit on the stage following the differential amplifier included in amplify/output circuit 240 described later.
Referring to FIG. 16, amplify/output circuit 240 includes an input circuit 1402, an equalizer circuit 1404, a differential amplifier 1406, inverters 1408-1414 and latch circuits 1416, 1418.
Input circuit 1402 includes an inverter 1422 and P-channel MOS transistors P1 and P2. Input circuit 1402 connects I/O line pair LIO and /LIO respectively to differential amp nodes PAN and /PAN to transmit data on I/O line pair LIO and /LIO to differential amp nodes PAN and /PAN, when signal PADT goes to H level.
Equalizer circuit 1404 includes P-channel MOS transistors P3 and P4. Equalizer circuit 1404 equalizes differential amp nodes PAN and /PAN to H level when signal /PAEQ is at L level.
Differential amplifier 1406 includes P-channel MOS transistors P5-P7 and N-channel MOS transistors N3-N5. Differential amplifier 1406 is activated by signals PAE and /PAE and amplifies small amplitude signals on differential amp nodes PAN, /PAN transmitted from I/O line pair LIO and /LIO through input circuit 1402 to provide signals fully swinging between a power supply voltage and a ground voltage.
Inverter 1408 includes P-channel MOS transistors P8 and P9 and an N-channel MOS transistor N6. Inverter 1408 is activated along with differential amplifier 1406 when signal /PAE is at L level, and inverts and outputs the signal on differential amp node PAN to a node ND3.
Inverter 1410 includes P-channel MOS transistors P10 and P11 and an N-channel MOS transistor N7. Inverter 1410 is activated when signal /PAEC is at L level, and inverts and outputs the signal on node ND3 to a node ND4.
Latch circuit 1416 includes inverters 1424 and 1426. Latch circuit 1416 latches the signal on data line PD3 for a period during which signal /PAEC generated by /PAEC generation circuit 138 is at H level after differential amplifier 1406 amplifies the signals on differential amp nodes PAN and /PAN and is then inactivated (signal PAE goes to L level), that is, until signal PACL goes to H level in order to read the next read data.
Then, when signal PACL goes to H level, signal CLRES output from CLRES generation circuit 136 goes to H level and signal /PAEC output from /PAEC generation circuit 138 goes to L level (at this point, signal PAE is at L level until signal PAEL goes to H level), so that latch circuit 1416 resets data line PD3 at L level at this timing.
Inverter 1412 includes P-channel MOS transistors P12 and P13 and an N-channel MOS transistor N8. Inverter 1412 is activated along with differential amplifier 1406 when signal /PAE is at L level, and inverts and outputs the signal on differential amp node /PAN to a node ND5.
Inverter 1414 includes P-channel MOS transistors P14 and P15 and an N-channel MOS transistor N9. Inverter 1414 is activated when signal /PAEC is at L level, and inverts and outputs the signal on node ND5 to a node ND6.
Latch circuit 1418 includes inverters 1428 and 1430. Similar to latch circuit 1416, latch circuit 1418 also latches the signal on data line /PD3 for a period during which signal /PAEC is at H level after differential amplifier 1406 amplifies the signals on differential amp nodes PAN and /PAN and is then inactivated, that is, until signal PACL goes to H level in order to read the next read data.
Then, when signal PACL goes to H level, signal CLRES output from CLRES generation circuit 136 goes to H level and signal /PAEC output from /PAEC generation circuit 138 goes to L level, so that latch circuit 1418 resets data line /PD3 to L level at this timing.
FIGS. 17 and 18 are circuit diagrams showing a circuit configuration of latency shifter 124. Latency shifter 124 includes an RDT input circuit 152 and a shift circuit 154.
Referring to FIG. 17, RDT input circuit 152 includes an inverter 1522 receiving and inverting signal RDT and outputting signal /RDT, an NOR gate 1524 receiving signal CLRES output from CLRES generation circuit 136 described above and signal /RDT to output signal RDSFT, and an inverter 1526 receiving and inverting signal RDSFT and outputting signal /RDSFT.
As described above, signal RDT received from the control circuit (not shown) is a signal for determining the timing for outputting the read data amplified by amplifier circuit 222 onto data bus pair DB and /DB. Signal RDT is generated starting from a clock cycle following a clock cycle that is a starting point of generating column decode enable signal CDE. More specifically, the data read from the memory cell array from a clock cycle #0 as a starting point is output onto data bus pair DB and /DB from a clock cycle #1 one cycle after clock cycle #0, as a starting point. Therefore, the read data shifts to the next stage in the pipeline.
Signal RDSFT generated by RDT input circuit 152 is at H level when signal CLRES and signal RDT are respectively at L level and H level. At this point, an inverter on an input stage in a shift circuit 154 described later is inactivated and an inverter latching the signals on data line pair /PD4 and PD4 in shift circuit 154 is activated. More specifically, when signal RDT providing a timing for outputting the read data onto data bus pair DB and /DB goes to H level, latency shifter 124 is isolated from amplifier circuit 222 in response to signal RDSFT and the signal taken-in from amplifier circuit 222 by latency shifter 124 is latched at this time point. Furthermore, signal /RDT is an inverted signal of signal RDT for providing a timing for outputting data received from amplifier circuit 222 by shift circuit 154 onto data line pair PDD and /PDD in shift circuit 154 described later.
Shift circuit 154 includes inverters 1542-1564.
Inverter 1542 receives the signal on data line PD3 and inverts and outputs the signal on data line PD3 to data line /PD4 when signal RDSFT is at L level (signal /RDSFT is at H level). Inverter 1544 receives and inverts the signal on data line /PD4. Inverter 1546 receives the output from inverter 1544 and inverts and outputs the received signal to data line /PD4 when signal RDSFT is at H level (signal /RDSFT is at L level). Inverters 1544 and 1546 form a latch circuit when signal RDSFT is at H level, so that the signal on data line /PD4 is latched.
Inverter 1548 receives the signal on data line /PD4 and outputs the signal on data line /PD4 to data line PDD when signal /RDT goes to L level (that is, signal RDT is at H level). Furthermore, inverter 1548 keeps data line PDD at L level when signal /RDT is at H level (that is, signal RDT is at L level). Inverter 1550 receives and inverts the signal on data line PDD. Inverter 1552 receives and inverts the output from inverter 1550 for output onto data line PDD.
Inverter 1548 includes P-channel MOS transistors P16 and P17 and an N-channel MOS transistor N10. P-channel MOS transistor P16 is connected to a power supply node VDD and P-channel MOS transistor P17 and has its gate connected to data line /PD4. P-channel MOS transistor P17 is connected to P-channel MOS transistor P16 and data line PDD and receives signal /RDT at its gate. N-channel MOS transistor N10 is connected to data line PDD and a ground node GND and receives signal /RDT at its gate. Furthermore, inverters 1550 and 1552 form a latch circuit, so that the signal on data line PDD is latched.
Inverter 1554 receives the signal on data line /PD3 and inverts the signal on data line /PD3 for output onto data line PD4 when signal RDSFT is at L level (signal /RDSFT is at H level). Inverter 1556 receives and inverts the signal on data line PD4. Inverter 1558 receives the output from inverter 1556 and inverts the received signal for output onto data line PD4 when signal RDSFT is at H level (signal /RDSFT is at L level). Inverters 1556 and 1558 form a latch circuit when signal RDSFT is at H level, so that the signal on data line PD4 is latched.
Inverter 1560 receives the signal on data line PD4 and outputs the signal on data line PD4 onto data line /PDD when signal /RDT goes to L level (that is, signal RDT is at H level). Furthermore, inverter 1560 keeps data line /PDD at L level when signal /RDT is at H level (that is, signal RDT is at L level). Inverter 1562 receives and inverts the signal on data line /PDD. Inverter 1564 receives and inverts the output from inverter 1562 for output onto data line /PDD.
Inverter 1560 includes P-channel MOS transistors P18 and P19 and an N-channel MOS transistor N11. P-channel MOS transistor P18 is connected to power supply node VDD and P-channel MOS transistor P19 and has its gate connected to data line PD4. P-channel MOS transistor P19 is connected to P-channel MOS transistor P18 and data line /PDD and receives signal /RDT at its gate. N-channel MOS transistor N11 is connected to data line /PDD and ground node GND and receives signal /RDT at its gate. Furthermore, inverters 1562 and 1564 form a latch circuit, so that the signal on data line /PDD is latched.
Now, as signal CLRES generated in CLRES generation circuit 136 of amplifier circuit 222 goes to H level, signals RDSFT and /RDSFT go to L level and H level, respectively, so that inverters 1542 and 1554 are activated. At this time point, the signals on data line pair PD3 and /PD3 reset at L level by signal CLRES at this point are inverted by inverters 1542 and 1554 and data line pair /PD4 and PD4 are reset at H level. More specifically, signal CLRES goes to H level previously before signal PAE activating differential amplifier 1406 goes to H level, and therefore data line pair /PD4 and PD4 are reset before differential amplifier 1406 is activated. Then, inverters 1542 and 1554 receive the respective read data output from amplifier circuit 222 onto data line pair PD3 and /PD3 and inverts the respective data to be output onto data line pair /PD4 and PD4.
Thereafter, when signal RDT goes to H level, signals RDSFT and /RDSFT go to H level and L level, respectively, so that both inverters 1542 and 1554 are inactivated. On the other hand, both inverters 1546 and 1558 are activated and the signals on data line pair /PD4 and PD4 are latched by inverters 1546 and 1558. Then, signal /RDT goes to L level in response to signal RDT going to H level, so that inverters 1548 and 1560 are activated and the signals on data line pair /PD4 and PD4 are inverted to be output onto data line pair PDD and /PDD, respectively.
FIG. 19 is a circuit diagram showing a circuit configuration of driver 126.
Referring to FIG. 19, driver 126 includes a one-shot pulse generation circuit 162, a DB drive circuit 164 and a /DB drive circuit 166.
One-shot pulse generation circuit 162 includes an NOR gate 168 receiving the signals on data line pair PDD and /PDD, a delay circuit 170 receiving and delaying the output from NOR gate 168, an inverter 172 receiving and inverting the output from delay circuit 170, and an inverter 174 inverting the output from inverter 172 to output onto a node ND9.
One-shot pulse generation circuit 162 further includes P-channel MOS transistors P20-P23 and N-channel MOS transistors N12-N14. P-channel MOS transistor P20 is connected to power supply node VDD and a node ND7 and has its gate connected to data line PDD. N-channel MOS transistor N12 is connected to node ND7 and a node ND10 and has its gate connected to data line PDD. P-channel MOS transistor P21 is connected to power supply node VDD and node ND7 and has its gate connected to node ND9. P-channel MOS transistor P22 is connected to power supply node VDD and a node ND8 and has its gate connected to data line /PDD. N-channel MOS transistor N13 is connected to node ND8 and node ND10 and has its gate connected to data line /PDD. P-channel MOS transistor P23 is connected to power supply node VDD and node ND8 and has its gate connected to node ND9. N-channel MOS transistor N14 is connected to node ND10 and ground node GND and has its gate connected to node ND9.
The operation of one-shot pulse generation circuit 162 will now be described.
In one-shot pulse generation circuit 162, when both of the signals on data line pair PDD and /PDD are at L level, P-channel MOS transistors P20 and P22 are turned on and N-channel MOS transistors N12 and N13 are turned off. Therefore, both signals /DRV and //DRV output respectively to nodes ND7 and ND8 are at H level. Furthermore, as the output of NOR gate 168 goes to H level, the signal on node ND9 goes to H level and N-channel MOS transistor N14 is turned on.
In this state, when the signal on data line PDD goes to H level, P-channel MOS transistor P20 and N-channel MOS transistor N12 are turned off and on, respectively, so that node ND7 is pulled down by N-channel MOS transistors N12 and N14 and signal /DRV on node ND7 goes to L level. On the other hand, as the output of NOR gate 168 goes to L level, the signal on node ND9 goes to L level after being delayed by a prescribed time of delay circuit 170. Accordingly, P-channel MOS transistor P21 is turned on and N-channel MOS transistor N14 is turned off, so that node ND7 is pulled up by P-channel MOS transistor P21 and signal /DRV on node ND7 is returned to H level. In other words, signal /DRV on node ND7 is at L level for a delay time period of delay circuit 170. It is noted that signal //DRV on node ND8 is always at H level during this time period.
Similarly, when the signal on data line /PDD goes to H level, signal //DRV on node ND8 is at L level for a delay time period of delay circuit 170.
It is noted that one-shot pulse generation circuit 162 is provided in order to reduce power consumption by outputting the signals from DB drive circuit 164 and /DB drive circuit 166 respectively onto data bus pair DB and /DB at small amplitude.
DB drive circuit 164 includes a P-channel MOS transistor P24, an inverter 176 and an N-channel MOS transistor N15. P-channel MOS transistor P24 is connected to power supply node VDD and data bus DB and has its gate connected to node ND7. Inverter 176 receives and inverts the signal /DRV on node ND8. N-channel MOS transistor N15 is connected to data bus DB and ground node GND and receives the output from inverter 176 at its gate.
In DB drive circuit 164, when signal /DRV on node ND7 and signal //DRV on node ND8 are respectively at L level and at H level, that is, when the signal on data line PDD goes to H level, P-channel MOS transistor P24 and N-channel MOS transistor N15 are turned on and off, respectively, so that data bus DB is pulled up to H level. Here, signal /DRV is a one-shot pulse signal being at L level for a delay time period of delay circuit 170, and P-channel MOS transistor P24 is turned off after this delay time period. Therefore, a signal having small amplitude is output onto data bus DB.
/DB drive circuit 166 includes a P-channel MOS transistor P25, an inverter 178 and an N-channel MOS transistor N16. P-channel MOS transistor P25 is connected to power supply node VDD and data bus /DB and has its gate connected to node ND8. Inverter 178 receives and inverts the signal /DRV on node ND7. N-channel MOS transistor N16 is connected to data bus /DB and ground node GND and receives the output from inverter 178 at its gate.
In /DB drive circuit 166, when signal /DRV on node ND7 and signal //DRV on node ND8 are respectively at H level and at L level, in other words, when the signal on data line PDD goes to H level, P-channel MOS transistor P25 and N-channel MOS transistor N16 are turned on and off, respectively, so that data bus /DB is pulled up to H level. Here, signal //DRV is a one-shot pulse signal being at L level for a delay time period of delay circuit 170, and P-channel MOS transistor P25 is turned off after this delay time period. Therefore, a signal having small amplitude is output onto data bus /DB.
FIG. 20 is a timing chart showing waveforms of representative signals in the circuits from bit line pair BL and /BL to data bus pair DB and /DB as described above.
Referring to FIG. 20, it is assumed that READ command is received at the rise of clock cycle #0. Column decode enable signal CDE is generated starting from the rise of clock cycle #0. Column select line CSL is activated by column decode enable signal CDE. When column select line CSL is activated, a small amplitude signal is output from sense amplifier 50 through N-channel MOS transistors N1 and N2 onto I/O line pair LIO and /LIO. Furthermore, either of signals PACL and PAEL has a generation timing determined based on column decode enable signal CDE as a starting point.
Signal PACL goes to H level after being delayed by a delay time of delay circuit 104 with respect to column decode enable signal CDE. CLRES generation circuit 136 outputs signal CLRES at H level in response to signal PACL going to H level. Internal nodes within preamplifier 148 such as data line pair PD3 and /PD3, data line pair /PD4 and PD4 and data line pair PDD and /PDD are reset. Furthermore, in response to signal PACL going to H level, input processing circuit 132 outputs signal /PAEQ at H level and equalizer circuit 1404 is inactivated.
Signal PAEL goes to H level after being delayed by a delay time of delay circuit 106 with respect to signal PACL. For a period from H level of signal PACL to H level of signal PAEL, input processing circuit 132 outputs signal PADT at H level. Responsively, input circuit 1402 in amplify/output circuit 240 connects I/O line pair LIO and /LIO respectively to differential amp nodes PAN and /PAN and data on I/O line pair LIO and /LIO is input into preamplifier 148.
Furthermore, when signal PAEL goes to H level, PAE generation circuit 234 outputs signals PAE and /PAE respectively at H level and L level. Responsively, differential amplifier 1406 is activated and the small amplitude signals on differential amp nodes PAN and /PAN are amplified to full amplitude. The signals on differential amp nodes PAN and /PAN are then transmitted onto data line pair /PD4 and PD4 via data line pair PD3 and /PD3.
The data transmitted onto data line pair /PD4 and PD4 are output onto data line pair PDD and /PDD in response to signals RDT and /RDT and one-shot pulse generation circuit 162 generates pulse signals /DRV and //DRV. In response to pulse signals /DRV and //DRV, DB drive circuit 164 and /DB drive circuit 166 are driven and data is output with small amplitude signals onto data bus pair DB and /DB.
Propagation of read data described above is carried out such that N-th (N is a natural number) data read out from the memory cell array is propagated from the memory cell array to data line pair /PD4 and PD4, starting from external clock CLK (Nxe2x88x921) cycles after external clock CLK receiving READ command. More specifically, the first output data is triggered by column decode enable signal CDE generated starting from clock cycle #0 in which READ command is received, and reaches data line pair /PD4 and PD4.
On the other hand, signals RDT and /RDT determining a timing for outputting data arriving on data line pair /PD4 and PD4 onto data bus pair DB and /DB are generated starting from external clock CLK one cycle after external clock CLK that is a starting point of column decode enable signal CDE. More specifically, signals RDT and /RDT determining a timing for outputting data read out from the memory cell array for the first time onto data bus pair DB and /DB are generated starting from clock cycle #1 following clock cycle #0 receiving READ command. Therefore, at the time data is output onto data bus pair DB and /DB, the timing is shifted by one cycle and data is moved onto the next stage in the pipeline.
The circuit operation as described above realizes the pipeline operation in a situation where data read from the memory cell array is output onto data bus pair DB and /DB. In case of CAS latency CL of 2.0, assuming that one stage of the pipeline is from data bus pair DB and /DB to a parallel/serial conversion circuit, if DLL clock received by the output buffer ultimately outputting the read data to the outside corresponds to external clock CLK two cycles after external clock CLK that is a starting point of column decode enable signal CDE, the read data is output from the parallel/serial conversion circuit to the output buffer in synchronization with DLL clock, so that the read data is output from the memory cell array to the outside precisely for two cycles.
Assuming that the timing of receiving READ command is provided in clock cycle #0, Tb represents the time required for the N-th read data to arrive on data line pair /PD4 and PD4 from the rise of clock cycle # (Nxe2x88x921) that is a starting point of reading that read data, and Tc represents the time required to generate signal /RDT in preamplifier 148 from clock cycle #N that is a starting point of signal RDT determining the timing of outputting the read data arriving on data line pair /PD4 and PD4 onto data bus pair DB and /DB. (In FIG. 20, a case where N=1 is shown.)
As signal /RDT is generated from signal RDT, signal /RDT corresponding to the N-th read data is generated (Tck+Tc) after external clock CLK which is a starting point of reading that read data, where Tck represents the period of external clock CLK.
Here, if the operation frequency is high and Tb greater than (Tck+Tc), in other words, if Tck less than (Tbxe2x88x92Tc), signal /RDT is generated in preamplifier 148 before the read data arrives on data line pair /RD4 and RD4. In this case, the timing at which the read data is output onto data bus pair DB and /DB is not provided on the falling edge of signal /RDT but at the timing when the read data propagates from data line pair PD3 and /PD3 onto data line pair /PD4 and PD4.
Then, a number of circuit elements exist until the read data arrives on data line pair /PD4 and PD4 after signal PAE goes to H level and differential amplifier 1406 starts operating. Therefore, a long waiting time occurs from H level of signal RDT to the actual reading of the read data onto data bus pair DB and /DB. This means that the time for the read data to propagate in the next stage is progressively longer if period Tck of external clock CLK is shorter than a certain time period. Therefore, the conventional circuit configuration cannot support a sufficient high frequency operation.
Therefore the present invention is made to solve such a problem. An object of the present invention is to provide a semiconductor memory device with faster propagation of read data from a preamplifier onto a data bus pair in a high frequency operation.
In accordance with the present invention, a semiconductor memory device is provided in which data is input/output in synchronization with a rise and a fall of an external clock. The semiconductor memory device includes: a memory cell array storing data; a control circuit producing first and second signals starting based on an adjacent clock cycle as a starting point; a preamplifier amplifying read data read from the memory cell array for output onto a data bus based on the first and second signals; and a data output circuit externally outputting the read data output onto the data bus. The preamplifier amplifies a signal level of the read data based on the first signal and outputs the read data having the amplified signal level onto the data bus based on the second signal when a timing of receiving the second signal is later than a timing of receiving the first signal, and amplifies a signal level of the read data based on the first signal and outputs the read data having the amplified signal level onto the data bus based on the first signal when a timing of receiving the second signal is earlier than a timing of receiving the first signal.
Preferably, the preamplifier includes an amplifier circuit receiving the first and second signals to amplify a signal level of the read data based on the first signal, a data shift circuit receiving the second signal to shift the read data having the signal level amplified by the amplifier circuit based on the second signal, and a driver outputting the read data onto the data bus. When a timing of receiving the second signal is later than a timing of receiving the first signal in the amplifier circuit, the amplifier circuit outputs the read data having the amplified signal level to the data shift circuit and the data shift circuit outputs the read data shifted based on the second signal to the driver. When a timing of receiving the second signal is earlier than a timing of receiving the first signal in the amplifier circuit, the amplifier circuit outputs the read data having the amplified signal level to the driver based on the first signal.
Preferably, the amplifier circuit further outputs the read data having the amplified signal level to the driver based on the second signal when a timing of receiving the second signal is later than a timing of receiving the first signal, and further outputs the read data having the amplified signal level to the data shift circuit based on the first signal when a timing of receiving the second signal is earlier than a timing of receiving the first signal.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.